高通qcc3034芯片datasheet與原理圖

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Switch mode regulators
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
1 ^8 s1 i* A+ j/ o7 `8 |receive power from VBAT or VCHG under application software control.
The System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
VFBGA and the flash memory. The System SMPS can supply power to external components.
8 f, @: R$ g, D: R* ~( K* IThe digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
3 A( J+ ]; F) N$ s  P/ A  Lbetween 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
The SMPS both have three operating modes:
5 P  o$ i0 ]/ x" ~0 |. E■ Normal (PWM)
+ P  E% P3 [" n8 S0 ]■ Two low-power modes with reduced current capability:
□ PFM
$ \9 m/ z% B4 j$ a0 j/ z□ ULP
/ U* y* V( x* ONormally the system auto switches, but this is optionally disabled.
) R5 h6 w4 W9 l$ I/ g  ^The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
For guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
3 F: C8 a$ b8 r4 MCH285-1).
8 }! {5 v1 w9 N3 WA single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have
3 H+ [& K( e! B) k$ ba 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.
6 \8 o) Z( C! N( Q$ jThe SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.

4 V$ C- D, B: S3 h6 x+ ?

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