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This application note is intended to provide recommendations concerning incorporation of circuit
6 E) T5 d' I6 ]5 b& {. r+ Lprotection devices and PCB layout guidelines to enhance an application's immunity in electrically noisy
0 o" D6 R, N7 _5 cenvironments and survivability of EMI, EMC, EFT, and ESD events as described in the International: s5 V, \9 D( j+ e
Electrotechnical Commission (IEC) standards: IEC 61000-4-2, IEC 61000-4-4, and IEC 61000-4-5.& z# o, w5 N$ ?5 M; ]# m9 W0 V8 x
We will begin with:
/ {- l# p+ Q4 q( S! j' ?# V1. A brief review of EMI, EFT, and ESD specifications.& L" A1 K" | \
2. Key ESD protection device specifications definitions.
4 @" e. R7 I! E3. A quick summary of EMI, EFT, and ESD protection strategies.* c7 @8 P5 `$ s0 m$ a" @
4. Capacitor filter selection and characteristics.0 u, U, I+ L, q% _) C. q4 Z% B
5. PCB Hardware design best practices and layout considerations checklists:
4 U9 f) b6 d& }" v. e+ H– Standard PCB design/layout practices$ V4 A; `- v& d4 ?8 Y" w9 {
– Special Ethernet layout considerations7 i4 ^; z5 H$ V6 ^2 H1 L
– Special DDR Layout considerations
( B+ r& u: a9 _" ]7 W6. Software protection techniques.4 q( T1 X8 S& l. B& x& ~
7. Microcontroller reference circuit schematics with protection examples:- Z- A; y, `' [5 p( S
– RS-232
. f5 v3 W& T( z4 S0 `$ M& U+ d– USB
8 g5 v1 V3 {4 |8 n2 M# R– CAN FD and LIN- Q* A" L5 j% ]2 Z/ z1 b/ L! U
– Ethernet
3 y8 P# L- o/ Z' @– Audio and mechanical switches
, w" h( A4 ], u& K2 l– LCD
& Y* w4 B8 B7 v7 b! U3 J, h– Power supplies
0 ]( J- e, I8 p& g– Reset and ICSP programming interface
+ k7 q! [/ P; v– SD memory card5 s; [' C- ]* K7 [' F) w
– I2C
) |' O; f+ U N$ A! {Reference Designs Note:
5 u3 ^) p4 e4 ~. @! q% sCost pressure is a constant consideration in any design. All of the circuit components in support of the. U7 [' N! q) [+ N- a6 z. q& b
CPU were selected based on the lowest cost and availability, which met the threat protection
4 M1 d6 V* f: \/ b" i* K/ F* srequirements. A user should carefully consider any substitutions. It is also highly recommended that the
$ G) n: `7 r( |0 n0 g% s3 x' |user consider designing in the protection elements in their layout, and then depopulate with zero ohm" Q% T- T$ e; G# g' a# d* t4 W) z
resistors as they think necessary, based on ESD, EMI, and EFT prototype board testing. This will save
6 Q" D, o& {. h' e$ Zsignificant board redesign time to market in the final product. |
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